This project presents the ASIC design flow implementation of a 16-point Fast Fourier Transform (FFT) architecture using a fully digital design methodology. The FFT algorithm is modeled and verified using Verilog HDL in the Xilinx Vivado environment, enabling functional simulation and verification of the design at the RTL level. The synthesized netlist is then passed through the OpenLANE physical design flow using SkyWater 130nm open-source PDK to perform logic synthesis, floorplanning, placement, clock tree synthesis, and routing. Post-layout views are analyzed using KLayout and Magic VLSI to inspect the physical layout and ensure design rule compliance and correctness. This end-to-end ASIC design process showcases a practical understanding of digital signal processing architecture, RTL design, and back-end VLSI implementation using open-source EDA tools and technology nodes. The project serves as a foundational step toward mastering custom ASIC design targeting real-world signal processing applications.