Executive Project Report 

Mentors 

Abhiram Chivukula, Aryan Manoj Murthy

Mentees 

Abhinith D, Kushal Gowda CR, Ritapragya Biswas, Sanskrati Saxena

Aim

This project aims to build a circuit design that would generate HSYNC, VSYNC, and the bitstream for red, blue, and green components of an image stored on an EPROM for the VGA pin inputs and thereby display the image stored on the EEPROM on the monitor 

Introduction

A video card is an integrated circuit that generates the video signal sent to a computer display. The card is usually located on the computer motherboard or is a separate circuit board but is sometimes built into the computer display unit. In modern computers, it also encompasses the GPU(Graphics processing unit). 

Our implementation of video card used counters(74LS161),nand gates(74HC30 and 74HC00) and inverter (74HC04) to generate the required video signals with a 10MHz crystal oscillator and an EPROM circuit to provide the RGB bitstream which is ported out to the monitor through a VGA adapter and cable, where VGA, Video Graphics Array is a standard type of connection for video devices such as monitors and projectors, just like an HDMI.

Methodology

The video card loads in the image information pixel by pixel, much like a cathode ray monitor, displaying each pixel in a horizontal line and then wrapping around to the next line after reaching the end of the screen.

To achieve this we use two main subcircuits, one for HSYNC and one for VSYNC. The HSYNC and VSYNC govern at which pixel the monitor wraps to the next line and when to wrap to the start of the screen respectively.

Both the signals comprise the display, front porch, sync signal, and back porch. The combination of the latter 3 signals governs the wrapping of pixels on the screen. Equipped with this information, the VGA appropriately loads the image onto the screen. 

To achieve this we use two main subcircuits, one for HSYNC and one for VSYNC. The HSYNC and VSYNC govern at which pixel the monitor wraps to the next line and when to wrap to the start of the screen respectively.

Both the signals comprise the display, front porch, sync signal, and back porch. The combination of the latter 3 signals governs the wrapping of pixels on the screen. Equipped with this information, the VGA appropriately loads the image onto the screen. To

Implementation

This project aims to display an image of resolution 200x600 pixels from an EEPROM onto the display monitor.

Here the display portion of the HSYNC and VSYNC signals extend till the 200th and the 600th pixel respectively. The front porch, sync signal, back porch  occur after these pixels as shown below in the table.

To keep track of different parts of the HSYNC and VSYNC signals, and display the correct pixels on the monitor, our project implements the following modules.

• Counter module(HSYNC and VSYNC counters) 
• NAND array
• SR Latches
• EEPROM
• VGA

Modules

HSYNC Counter Module

We use 3 IC74161 4 bit counters to keep track of the HSYNC signal and which individual pixel on the horizontal line needs to be pushed onto the monitor display.

 With each count-up that the counter produces, a single pixel is pushed onto the monitor. The counters run on a  oscillator clock of frequency 10MHz, that is one pixel is pushed per 1 nanosecond. The counter resets after reaching a value of 264 as per the timing diagram.

With the above timing diagram the HSYNC signal produced is 3.2 us and the circuit designed produces one that is 3.4us long, approximately equal to the theoretical correct value 

VSYNC Counter Module

Much like the HSYNC counter module, the VSYNC counter module also uses 3 IC74161 4-bit counters to keep track of the HSYNC signal and the line that the pixels are being pushed onto.

 But in this case, the clock provided to the 74161 counter ICs in this module is the signal produced by the HSYNC module on reaching the end of the back porch. This makes it such that VSYNC counts up only when the HSYNC counter goes through one iteration, ie, the pixel pointer moves to the next horizontal line only after the end of the previous horizontal is reached.

 The VSYNC counter module resets after reaching a value of 628 as per the timing diagram.

The VSYNC signal produced in this case is of length 104us, approximately equal to the 105.6us which was the theoretical signal to be achieved.

Both the modules are combined with NAND gate arrays to produce the front porch, back porch, and sync signal, which tells the VGA at what coordinate of the screen display the pixel at.

NAND Gate Array

To use the counters to produce the front porch, back porch and sync signals, an array of NAND gates are used to produce a signal when the counters reach the critical points in the timing diagram.

For each of the HSYNC and VSYNC counter modules, we use 4 IC7400 quad 2-input NAND gates. These NAND gates are connected to specific pins on each of the individual counter ICs of the counter modules, such that they produce distinct pulses when the front porch, back porch, and sync signal regions of the timing diagram are reached.

This includes producing the LOW sync signal at 242 pixels for HSYNC, and 605 pixels for VSYNC and producing a LOW signal when the end of the back porch is encountered at 264 pixels for HSYNC, and 628 pixels for VSYNC. The latter two signals are wired to active low CLEAR pins of the individual IC74161 counters so that they reset after the end of the pixel line is reached in the case of HSYNC, and after the end, the vertical screen is reached in the case of VSYNC.

SR Latches

To produce the sync signals for the VGA a pair of SR Latches are used. For the HSYNC signal, the latch is set at 210 pixels and reset at 242 pixels. Similarly, for the VSYNC signal, the latch is set at 601 pixels and reset at 605 pixels

EEPROM

The EEPROM is used to store read only data of a single image which, with the help of the timing circuit created, displays the image on the monitor screen.

The binary count from both the counters is fed into the address pins of the EEPROM, such that each combination of the horizontal and the vertical counter gives the address where the data of that specific pixel is stored.

The range of each of the RGB values should be between 0V and 0.7V, with 0.7V being the maximum brightness of that colour.

The output for each of these addresses is taken across six bits, two for each red,blue and green value, which results in 4 combinations, ie, 4 different shades of each RGB value. To do this each of the two bits are connected to resistors of values 1.5k and 680 ohm, such that depending on their combinations they produce a 4 distinct colour shades between the range 0V to 0.7V

VGA Communication

The HSYNC, VSYNC, RGB data, are fed into the VGA port and the respective ground pins are set to GND.

The VGA is then connected to the monitor screen. The entire circuit runs on a 10MHz clock, and if the the respective sync signals are appropriately timed, then the monitor recognizes the VGA signal and outputs whatever was stored in the EEPROM

Results

This breadboard video card is capable of displaying an image that is fed to it through an EEPROM after being converted into a binary file with the help of a binary script. This video card can display images of up to 200x600 resolution.

Conclusion

The project integrated various topics such as the use of counters to count pixels, combinational circuits that would be suitable for the VGA timing parameters, the functioning of an EEPROM, and finally the use of a VGA to display an image on the monitor.

Through the project, we gained a deep understanding of the fundamental principles underlying video signal generation. We were introduced to concepts such as horizontal and vertical synchronisation, pixel rendering, and VGA timing parameters.

Building the video card from scratch provided us with an invaluable hands-on experience in circuit design. Throughout the project, we encountered challenges and setbacks that allowed us to apply our problem-solving skills to their maximum potential.

Acknowledgements

We would like to extend my heartfelt gratitude to IEEE NITK for their support and sponsorship of our project, without which, this endeavour would not have been possible.

We would also like to thank our mentors for constant support and guiding our hand throughout the project.

References

1. Upadhyay R, Article on VGA Monitor Interfacing,  Vol 6, pp. 50 56, December 2022.
2. Mano M., Ciletti M., “Digital Design-Fourth Edition” United States: Prentice Hall, 2018
3. Beater.net and Ben Eater’s Youtube playlist  “The world’s worst video card”.