YEAR-2024

Summary: 

Following a RISC approach, this project implements a 32-bit, 5-stage MIPS processor in Verilog.Incorporating five pipeline stages.The 5 stages being used are Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory (MEM) and Write Back (WB). The instruction set being used is 32-bits. The various modules being used are Instruction Memory ,Data Memory, ALU, ALU Control, Control Unit, Registers etc.

Aim:

Design a functional and efficient 32-bit MIPS processor in Verilog. And generation of GDSII file from RTL.

Gain a deeper understanding of processor architecture and pipelining concepts.

Introduction: 

The project involves implementing a 32-bit 5-stage MIPS processor using Verilog, a widely-used hardware description language. The MIPS architecture is known for its efficiency and is commonly found in various embedded systems and microcontrollers. The design follows a RISC approach, focusing on simplicity and efficiency in instruction execution.

Methodology: 

The design incorporates five pipeline stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory (MEM), and Write Back (WB). Significant modules include the control unit, Arithmetic Logic Unit (ALU), register file, memory interface, and instruction and data memory modules. 

Instruction Fetch (IF):

• Retrieves the next instruction from memory using the program counter (PC).
• Stores the fetched instruction in the instruction register (IR).

Instruction Decode (ID):

• Decodes the instruction in the IR.
• Generates necessary control signals.
• Identifies the opcode and determines source/destination registers.

Execution (EX):

• Performs the operation specified by the instruction.
• ALU executes arithmetic and logical operations.
• Calculates branch addresses and memory addresses.
• Updates the PC with the branch address if applicable.

Memory Access (MEM):

• Handles memory access if the instruction involves it (load or store).
• Reads from or writes to data memory.

Write Back (WB):

• Writes the operation results back to the register file (RF).

Processor Specifications:

• Instruction Set Architecture (ISA): MIPS32
• Word Size: 32 bits
• Pipeline Stages: 5 (IF, ID, EX, MEM, WB)
• Instruction Types Supported: R-type, I-type, J-type

Instruction Types and Details:

R-type Instructions:

• Three operands: two source registers and one destination register.
• Used for arithmetic, logical, and shift operations.
• Examples: add, sub, and, or, xor

I-type Instructions:

• Two operands: one source register and one immediate operand.
• Used for loading, storing, branching, and immediate arithmetic/logical operations.
• Examples: lw, sw

J-type Instructions:

• One operand: a jump address.
• Used for unconditional jumps and subroutine calls.
• Examples: j

Comprehensive List of Instructions: For a complete listing of MIPS32 instructions and their details, refer to the MIPS32 Instruction Set Architecture (ISA) documentation.

Pipeline Stages:

IF:

• Fetch the instruction from memory using the PC.
• Increment the PC for the next instruction.

ID:

• Decode the instruction in the IR.
• Determine the opcode, operands, and control signals.
• Read operands from the RF.

EX:

• Perform the operation specified by the instruction in the ALU.
• Calculate memory addresses or branch addresses.
• Updates the PC with the branch address if applicable.

MEM:

• Access data memory if the instruction involves a load or store.
• Read data from memory (load) or write data to memory (store).

WB:

• Write the result of the operation back to the RF.

Verilog Implementation: The Verilog implementation of the pipelined MIPS processor would involve modules for each stage, along with interconnections and control logic. Each module would be responsible for its specific functionality within the pipeline.

Results:

The project successfully resulted in a functional 32-bit MIPS pipelined processor using Verilog.

Obtained Waveforms:

Addition

AND

            OR

         Set Less Than

Openlane GDSII file:

Conclusions:

This project provided valuable insights into processor architecture and pipelining. The implemented MIPS processor offers a solid foundation for further exploration and optimization in computer architecture and digital system design. The Verilog implementation allows for customization and extension with additional features.

Future scope:

 Exploring Openlane ways of synthesis optimisation

References:

[Maf01] Mafla, E. Course Notes, CDA3101, at URL http://www.cise.ufl.edu/~emafla/ (as-of 11 Apr 2001).

[MK98] Copyright 1998 Morgan Kaufmann Publishers, Inc. All Rights Reserved, per copyright notice request at http://www.mkp.com/books_catalog/cod2/cod2ecrt.htm (1998).

[Pat98] Patterson, D.A. and J.L. Hennesey. Computer Organization and Design: The Hardware/Software Interface, Second Edition, San Francisco, CA: Morgan Kaufman (1998).